Power devices have been widely used to carry large currents at high voltages. The problems with these devices included their large size and unreliability. However, in the early 1950's, developers of electronic power systems began to base their high power systems on semiconductor devices.
Many of these early semiconductor power devices included a single large device for handling large currents; e.g., a thyristor or rectifier. By the 1970's, devices were fabricated capable of operating at up to 3,000 volts and controlling 1,000 amperes of current. Other types of devices have also been fabricated which are adapted to carry large currents and voltages by connecting many small discrete devices, such as bipolar devices, in parallel. The bipolar devices were first developed in the early 1950's. Today it is possible to fabricate bipolar transistors with a current handling capability of several hundred amperes and a block voltage of 600 volts.
Bipolar transistors, however, have several major problems in their operation. For example, a high current is required to control the bipolar transistor, typically one-fifth to one-tenth of the collector current. Consequently, the base drive circuitry contains many intricate and expensive components. Bipolar transistors are also subject to a breakdown failure when high current and voltage are simultaneously applied to the device as required in inductive power circuits. Metal Oxide Semiconductor (MOS)-gated devices were suggested to solve these problems.
The MOS-gated power device overcomes many of the problems of bipolar devices. The control signal of a MOS-gated device is connected to a metal gate electrode that is separated from the semiconductor surface by an intervening insulator, typically silicon dioxide. Accordingly, MOS-gated devices have a high input impedance which allows for simpler gate drive circuitry and cost reduction within the power electronics. The power MOSFETs' switching speed is many orders of magnitude faster than the switching speed for bipolar transistors, thus making MOSFETs particularly suitable in high frequency circuits where switching power losses are frequent.
In many present day power devices, large numbers of parallel-connected individual bipolar, MOS or other devices, commonly referred to as "cells", are fabricated in parallel in a single semiconductor integrated circuit, using well known microelectronic manufacturing techniques. Presently, up to 100,000 or more individual low current MOS-gated cells may be fabricated in parallel to produce a power device.
A major concern in fabricating a high current power device containing a large number of parallel cells is the yield of the resulting chip. In particular, it is difficult to provide a high yield high current power device in view of the defect rate of the individual cells on the semiconductor substrate. Since these individual cells are electrically connected parallel to one another, a short circuit in one cell renders the power device unusable. Accordingly, in practice, yields of only 30% are typically obtained even for relatively small chips with size of 0.25 inch by 0.25 inch.
One attempt at overcoming this yield problem is described in the article "A Large Area MOS-GTO with Wafer-repair Technique" by Stoisiek, et al., IEDM, 1987, pages 666-669. In this approach a MOS power device is fabricated out of about 300,000 individual MOS cells on a semiconductor substrate. The individual MOS cells are grouped into cell blocks, and each cell block is individually tested for faulty operation. The substrate is covered with an insulating layer, and via hole pattern is etched into the insulating layer according to the results of the previous operational measurements, i.e. holes are etched only over the cell blocks without a fault. Consequently, the faulty cell blocks are insulated from the rest of the device. A metal layer connects all the operational cell blocks through the via holes. Thus, shorted cells are prevented from causing other cells to short circuit because they are not connected in parallel with the functional cells.
While the above described technique prevents a short circuit in one or more individual cell blocks from destroying the entire power device, this technique is not amenable to mass production of power devices. Each individual cell block must be tested for shorts, which is a time consuming process. Once shorts are identified, a custom mask must be designed for every wafer so that a via hole pattern may be etched on the insulating layer to connect only the fault-free cells or cell blocks. The cost of individual masks and the turn around time for designing the masks and then forming the individually designed via patterns makes the resultant devices prohibitively expensive. In addition, these operations increase the number of processing steps and add to overall fabrication cost for the large area device.